Cache memory indexing using virtual, primary and secondary color indexes

ABSTRACT

The memory device comprises a cache memory indexed by the cache index and group information of the virtual address. The physical address translated from the virtual address contains primary and secondary group information. If the tag of the cache entry addressed according to the above standard by indexing of the cache memory corresponds to the physical address, indexing is carried out again using the second group information associated with the physical address (and using the cache index of the virtual address). If the tag of the cache entry thus addressed still does not correspond to the physical address, a cache miss is signaled.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention refers to a cache memory with a virtually or physicallyindexed and physically tagged cache memory.

2. Description of Related Art

Modern processors require cache memories to bridge the gap between fastprocessors and slow main memories.

In direct mapped caches (see FIGS. 6 and 7), a map function is used forcomputing a cache index from the physical or virtual address a, thusselecting a line of the cache. Subsequently, a is compared with theaddress of the storage area currently associated with this cache line(the tag of the cache entry). Equality produces a hit (and the cacheline is used instead of the main memory), otherwise we get a miss.

In most cases (a mod cache size)/line size is used as a map function. Inthis case, the complete virtual address need not be stored in the cache,but a/cache size is sufficient.

Direct mapped caches are simpler, but lead to higher miss rates thann-way set-associative caches do. These caches consist in principle of ndirect mapped cache blocks which are accordingly smaller. Additionally,it is ensured that each main memory element is contained in at most oneblock. Since the map function indexes n cache lines each time, a maximumof n elements with map-equivalent addresses can be contained in thecache. This n-fold associativity reduces the probability of clashes andincreases the hit rate correspondingly.

Physically and virtually indexed caches are well-known. In the case ofthe physically indexed cache (FIG. 6), the virtual address delivered bythe processor is first translated into a physical address by thetranslation lookaside buffer (TLB). Subsequently, the cache is addressedusing the physical address.

In the case of the virtually indexed cache (FIG. 7), the cache isaddressed directly using the virtual address. A translation into thecorresponding physical address is done only upon cache miss. Theadvantage of a virtually indexed cache is higher speed since thetranslation step to be done by the TLB is not necessary. Itsdisadvantages appear in the case of synonyms (aliasing) and/ormultiprocessor systems.

Though a physically indexed cache does not show these disadvantages, itrequires a complete address translation step (virtual→physical) from theTLB prior to initiating a cache access.

The cache type favored nowadays is virtually indexed and realphysically) tagged. It is as fast as a virtually indexed and virtuallytagged cache, but avoids most disadvantages of the latter, in particularproblems with multiprocessor systems, synonyms, sharing and coherence.

A virtually indexed and physically tagged cache enables parallelexecution of TLB and cache access (see FIG. 8). The instruction pipelineof the processor is therefore shorter so that the latency of aninstruction is usually reduced by one cycle and the processor'sperformance is increased correspondingly.

The mechanism remains simple if all address bits (i) required for cacheindexing are in the area of the address offsets (address within a page).Since this address part is not modified by translating the virtualaddress into the physical address, the cache can be addressed (indexed)even before the TLB translation step. Only at the end of a cache accessand simultaneous TLB translation step, is it checked whether thephysical address associated with the cache entry (the tag) matches thephysical address delivered by the TLB. For this purpose, only thehigh-order bits of the address which are adjacent to the index part (i)need to be compared since the cache entry indexed by (i) can only beassociated with addresses having index bits of value (i). Accordingly,only the high-order bits have to be stored in the cache as tag (physicaladdress).

An n-way set-associative cache of this type can have a maximum size ofn×2^(P), where 2^(P) is the page size. Larger caches require largerpages or higher associativity.

However, a more interesting technique is page coloring. This is a methodof creating pages in the physical memory in such a way that thelow-order address bits of virtual and physical page addresses areidentical (see FIG. 9). Virtual page number (vpn) and cache index (i)overlap in this case. In FIG. 9, the overlapping part is represented asa black box. The corresponding part of the virtual address is calledvirtual color c, that of the physical address is called physical colorc'. Upon color-preserving allocation, i.e., if virtual color andphysical color are identical, the above mentioned size limitationn×2^(P) no longer holds.

If, as shown in FIG. 10, virtual and physical color are also compared,the color bits can be omitted when storing the tag (physical address)and only the high-order bits of the physical page number (r') have to becompared with the tag.

Of course, a cache should also work in the case of an allocation whichis not perfectly well-colored. If the first cache access leads thereforeto a miss and if the physical color c' delivered by the TLB is differentfrom the virtual color c, a color-corrected cache access would have tobe tried (see FIG. 11). Pages colored incorrectly can therefore be used,for accessing data in such a page, however, always an additional stepupon cache access would be required (see FIG. 12).

It is to be noted that badly-colored allocations cannot be avoided undercertain conditions, e.g. if two virtual pages of different colors haveto be mapped to the same physical page. This involves repeated colorcorrections, which is time-consuming and delays the cache access.

It is the object of the invention to build a cache that is virtuallyand/or physically indexed and physically tagged, and, even in case ofbadly-colored allocated pages, allows for a fast cache access and/orreduces the risk of clashes.

SUMMARY OF THE INVENTION

In order to solve this object a memory device with the features of claim1 is provided; features of advantageous embodiments are mentioned in therespective subclaims. In the present memory device, a secondary groupinformation ("secondary color") is associated to each physical addresstranslated from a virtual address, apart from a primary groupinformation (referred to above as "physical color"). Both informationelements are derived from the page tables, in particular by the MMUMemory Management Unit), and are written into the translation lookasidebuffer (TLB), if any should be used. If no tag of the addressed cacheentry or entries matches the physical address translated from thevirtual address and the group information ("virtual color") of thevirtual address does not match the secondary group information(secondary color) associated to the translated physical address, colorcorrection is executed by indexing the cache memory again using thecache index portion and the secondary group information and by comparingthe tag or tags of the addressed cache entry or entries with thephysical address translated from the virtual address.

In the present memory device, a cache access using a virtual address isattempted as follows:

a) First, a number of cache entries is addressed corresponding to theassociativity of the cache memory, by indexing the cache memory usingthe cache index and the group information which are both part of thevirtual address aor which are derived from the virtual address or fromparts thereof (FIG. 2).

Subsequently, the virtual address or, more specifically, its page numberaddress portion representing the virtual page number, is translated intoa physical address or, more specifically, a page number physical addressportion representing the physical page number. This page number physicaladdress portion includes the primary group information as one partthereof. Upon translation, the associated secondary group information isalso provided.

b) The physical address resulting from the translation of the virtualaddress is compared with the tag of each addressed cache entry.

The translation of the virtual address into the physical address isnormally done with a translation lookaside buffer (TLB) indexed by apart of the virtual address--possibly modified by a hash function--so asto compare the part of the virtual address used for indexing with thetag of the addressed TLB entry. In case of a match, the physical addressand the first and second group information are read from the TLB entry.If they differ, there is a TLB miss and the translation of the virtualaddress into a physical address is executed by the MMU using pagetables, for example (FIG. 1).

c) Upon a match of the translated physical address and the tag of theaddressed cache entry or one of the tags of the addressed cache entries,there is a cache hit and reading from the data field of the respectivecache entry, or writing into the data field, takes place, depending onwell-known status information and access control variables not detailedherein.

d) Otherwise, the cache memory is indexed again, using the cache indexof the virtual address and the secondary group information. It issuitable to perform this new indexing of the cache memory only if thevirtual group information does not match the secondary group informationassociated to the physical address. For the cache entry or entries thusaddressed, the steps b) and c) are repeated (FIG. 4).

e) If, after a new indexing operation, there still is no match betweenthe physical address and the tag or one of the tags, a cache miss isindicated and the access is aborted.

The invention allows for a better exploitation of main memories withlarge cache memories without the cache access times being increased.This is due to the fact that no longer only well-colored, but also otherdefined not well-colored allocations can be treated efficiently (via thesecondary group information). The secondary group information is of thepresent memory device is a random information, yet defined prior to theindexing of the cache memory, which information is provided inparticular by the TLB and/or the MMU which obtains or derives thesecondary group information from the page tables.

In case of inequality between the tag of the cache entry or entriesaddressed with the cache index portion and the group information,according to a modification of the above access (see claim 4), an accessby indexing the cache memory using the secondary group information andthe cache index portion of the virtual address will only be attempted ifthe secondary group information differs from the group information. Inany other case, the cache access is aborted and a cache miss issignaled. For the required comparison of the secondary group informationwith the group information, a group information comparison is provided.

In an alternative embodiment of the invention, after an access thatresulted in a cache miss, the cache memory is indexed anew with theprimary group information (and the cache index portion). This indexingnay be executed either directly after the first indexing using the groupinformation of the virtual address or after the indexing using thesecondary information.

Preferably, after the first indexing using the group information (andwhich did not result in a cache hit) and prior to the new indexing withthe primary or secondary group information, it is checked whether thesecondary group information differs from the group information orwhether it is identic with the group information. Should the secondarygroup information differ from the group information, the first newindexing (second indexing) is executed using the secondary groupinformation. If this second indexing did again not lead to a cache hit,a third indexing will be attempted thereafter, using the primary groupinformation (normal case). Should, however, the primary groupinformation differ from the secondary group information, while thesecondary group information and the group information are identical, theindexing operation using the secondary group information, which in facthad been attempted before with the first indexing and had not beensuccessful (group information and secondary group information areidentical), is skipped and the new indexing operation of the cachememory (also referred as the third indexing in analogy to the above) isexecuted using the primary group information (special case). In the twocases described above, the third indexing using the primary groupinformation is preferably executed only if the primary group informationdiffers from both the group information and the secondary groupinformation.

Alternatively, the second indexing is always attempted using the primarygroup information, so as to attempt the third indexing with thesecondary group information should there have been no cache hit. It isalso possible upon the first new indexing to select one of the twopossibilities, in particular under control by a random-check generator,i.e. to select either the second indexing using the secondary groupinformation and the third indexing using the primary group informationor the second indexing using the primary group information and the thirdindexing using the secondary group information. Instead of arandom-check generator, or in addition to the same, the choice of thetwo possibilities mentioned above can be made considering previous hits(cache hit) or misses (cache miss).

For a better exploitation of the space of a cache memory, an alternativeembodiment of the invention provides that the cache memory is indexed bya combination of the cache index portion of the (physical or virtual)address and an additional index, the additional index being associatedto the address while not being a part thereof. Choosing the additionalindex correspondingly, the indexing of the cache memory can bepurposefully influenced, which offers a chance for an improvedexploitation of the memory space. The additional index is provided,e.g., by a MMU and/or a TLB,-which also provide the physical address orthe portion of the address necessary for accessing the cache memory.

The appended claims 12 to 15 refer to variants of a cache memory arraywith a first- and second-level cache memory device of the abovementioned kinds according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The following is a detailed description of an embodiment of theinvention. In the Figures

FIG. 1 is a schematic illustration of the structure of a TLB as used inthe cache memory,

FIG. 2 shows the step of preparing the indexing of the cache memory,

FIG. 3 illustrates the first access step at the cache memory,

FIG. 4 shows the color correction step at the cache memory,

FIG. 5 illustrates a block diagram of a secondary color cache with asecondary color bus for connecting a plurality of secondary color cachememories,

FIG. 6 shows the structure of a physically indexed cache memory,

FIG. 7 illustrates the structure of a virtually indexed and virtuallytagged cache memory,

FIG. 8 shows the structure of a virtually indexed and physically taggedcache memory,

FIG. 9 illustrates the structure of a cache memory based on well-coloredallocation,

FIG. 10 shows the step of checking the well-coloring in the cache memoryof FIG. 9,

FIG. 11 illustrates the color correction step in the cache memory ofFIG. 9,

FIG. 12 illustrates the access step in the cache memory of FIG. 9 and

FIG. 13 shows a physically indexed cache with an additional indexassociated with the address.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The secondary color TLB, used for translating the virtual address intothe physical address, differs from conventional TLBs in that it not onlycontains virtual page number, physical page number and possibly statuscontrol information (not listed here) and access control information(access attributes) per entry but in addition one secondary color pervirtual page (see also FIG. 1). Upon a hit, the TLB delivers thephysical address (r',c) and the corresponding secondary color (c") .

It is irrelevant, whether the TLB is direct mapped, n-wayset-associative or fully associative. In the case of an n-wayset-associative TLB, n entries are selected simultaneously and theirvirtual addresses are compared with vpn in parallel. In the case of afully associative TLB, the hash and selection function is not used, andall TLB entries are simultaneously checked against vpn.

Independently of the used page table structure, a TLB entry is reloadedfrom the page table data structure upon a TLB miss. In this case, notonly physical address and access attribute but also the secondary colorare taken from the page table (i.e., at least each valid lowest levelpage table entry also contains the selected secondary color).

The secondary color can be selected freely by the operating system, inparticular in such a way that the above invariance condition alwaysholds. The following statement holds: if two TLB entries refer to thesame physical page address, their secondary colors match (invariancecondition).

The basic idea is to use always the secondary and not the primary(physical) color for allocation in the direct mapped or n-wayset-associative cache. Accesses via virtual addresses which match withthe secondary color are then fast; other ones need an additional colorcorrection step (in the case of c'=c", the system behaves like aconventional cache).

Notation (see also FIG. 2):

v virtual address

vpn virtual page number

c virtual color (group information of the virtual address)

rpn physical (real) page number

c' physical color, also referred to as primary color (primary groupinformation)

c" secondary color (secondary group information)

r' high-order part of rpn (without c')

c index color (the portion that is used for indexing the cache besidesthe index portion of the virtual address)

i low-order part of cache entry number

Each cache entry (line) contains a field r_(i) and a field c_(i) for thetag, a data field d_(i), as well as further status fields which are notlisted here.

A current cache line is selected by an index i whose high-order bits arereferred to as index color c. Virtual color, primary color, secondarycolor and index color have the same number of bits.

Step 1

At the beginning of a cache access, the index port (c, i) is loaded fromthe virtual address (see FIG. 2). Simultaneously, the TLB starts anaddress translation with vpn as input.

Step 2

The cache entry addressed through (c, i ) is read out. The physical pageaddress (r', c') delivered by the TLB is compared with the physicaladdress (r_(i), c_(i)) stored in the cache entry and the secondary colorc" also delivered by the TLB is compared with the index color c (FIG.3). If the physical addresses are identical ((r',c')=(r_(p) c_(i))), itis a cache hit, i.e., the data of the cache are delivered (read access)or the new data are written into the cache (write access). Then cacheaccess is finished. If the cache memory is n-way set-associative, thephysical address delivered by the TLB is compared in parallel with thephysical addresses contained in the n selected entries simultaneously. Acache hit is obtained if one comparison delivers a match. Thecorresponding entry is read out or modified, depending on accessattributes and status information.

Step 3

If step 2 did not yield any cache hit (in all cases (r', c')≠(r_(p)c_(i))) and if the index color differs from the secondary color (c≠c"),a color correction is tried (FIG. 4): c is loaded with secondary colorc" and step 2 is executed again.

Step 4

In any other case, cache access is aborted and a miss is signaled.

For reasons of clarity, only reading out and writing whole cache entrieshave been described. Considering low-order address bits, only parts ofan entry can of course also be read or written using the usual andwell-known procedures. There are no impacts on the control logicdescribed here.

Free allocation of cache entries by means of primary or secondary color(mixed even within one page) is enabled by modifying steps 2 and 3. Theprocedure is as follows:

Step 2

The cache entry addressed through (c, i) is read out. The physical pageaddress (r', c') delivered by the TLB is compared with the physicaladdress (r_(p), c_(i)) stored in the cache entry, the primary color c'is compared with the index color c and the secondary color c", alsodelivered by the TLB, is compared as well with the index color c. If thephysical addresses are identical ((r', c')=(r_(p) c_(i))), it is a cachehit, i.e., the data of the cache is delivered (read access) or the newdata is written into the cache (write access). Then the cache access isfinished.

Step 3

If step 2 did not yield any cache hit (in all cases ((r', c')≠(r_(i),c_(i))) and if there was not yet a detour step during this cache accessand

(a) if the index color is identical to the secondary color (c=c") and ifprimary and secondary color are different (c'≠c"), a detour isattempted: c is loaded with the primary color c', a detour step isrecorded and another step 2 is executed;

(b) or if the index color differs from the secondary color (c≠c"), acolor correction is attempted (FIG. 4): c is loaded with the secondarycolor c" and another step 2 is executed.

Variant 1

Primary color and secondary color exchange their roles:

Step 3

If step 2 did not yield any cache hit (in all cases ((r', c') ; (r_(p)c_(i))) and if there was not yet a detour step during this cache accessand

(a) if the index color is identical to the primary color (c=c') and ifprimary and secondary color are different (c'≠c"), a detour isattempted: c is loaded with the secondary color c", a detour step isrecorded; or

(b) if the index color differs from the primary color (c≠c'), a colorcorrection is attempted: c is loaded with the primary color c' andanother step 2 is executed.

Variant 2

If the virtual color equals neither the primary nor the secondary color,one casts dice for determining the sequence of trying c' and c":

Step 3

If step 2 did not yield any cache hit (in all cases ((r', c')≠(r_(p),c_(i))) and if there was not yet a detour step during this cache accessand

(a) if the index color is identical to the primary color (c=c') and ifprimary and secondary color are different (c'≠c"), a detour isattempted: c is loaded with the secondary color c", a detour step isrecorded and another stop 2 is executed; or

(b) if the index color is identical to the secondary color (c=c') and ifprimary and secondary color are different (c'≠c"), a detour isattempted: c is loaded with the primary color c', a detour step isrecorded and another step 2 is executed; or

(c) if the index color is different from primary and secondary color(c≠c' and c≠c"), a color correction is attempted by loading c with theprimary color c' or with the secondary color c" and another step 2 isexecuted.

The decision mechanism of item 3c can work randomly or considerpreceding hits and misses. A further variant is that, in addition to thesecondary color, the TLB also stores a strategy hint which is analyzedby the decision mechanism.

For multiprocessor systems with a plurality of processors and cachesdirectly associated therewith it holds that almost all cache coherenceprotocols require that not only the processor but also the memory busdelivers the secondary color in addition to the physical address (FIG.5). For implementation, the external address bus is extended by asecondary color bus. If the latter is used consistently, each coherenceprotocol working on conventional physically addressed caches can beimplemented without extra effort.

The cache of each processor places not only the physical address butalso the secondary color onto the bus. That is always possible becausethe secondary color is delivered by the TLB upon read accesses and canbe extracted from the cache index upon write accesses.

For multiprocessor systems, the problem is therefore solved if the pagetable trees of all processors contain no inconsistent secondary colorallocations, i.e., if the invariance condition mentioned above holdssystem-wide.

For reasons of consistency, bus masters which do not access via virtualaddresses, for example DMA or screen processors, should also support thesecondary color bus.

To take the physical color as a secondary color and to leave thesolution of the consistency problem to the operating system is thesimplest solution. The latter must then allocate such areasappropriately (secondary color =physical color) or otherwise it mustflush the caches before.

Such restrictions can be avoided by providing the correspondingcontrollers with secondary color information. When programming a DMAchip, one would program not only address and length per storage area,but also the secondary color.

Upon MMU accesses to the page tables, the TLB can deliver no secondarycolor information. However, such accesses can be executed using thephysical color as secondary color.

It is also possible to use a specific secondary color for this purposeor to read out the secondary color information together with the tableaddresses for the next step from the page table entries when parsing thetree. In this way, the allocation of cache entries for page tableinformation can possibly be controlled.

If the restriction that the secondary color of a physical area isidentical for all accessing processors, should be removed, a set ofsecondary colors can be stored in each page table entry instead of onesingle color. Each processor is extended by a register which indicateswhich entry of the secondary color set is applicable to the respectiveprocessor. (Consequently, the secondary color set can be by far smallerthan the number of the processors.)

The secondary color bus is then extended such that it provides a wholeset of secondary colors. However, for write back caches, the secondarycolor set must be stored in the cache. For write through caches, itsuffices if the TLB stores the respective set.

An alternative, but very costly method which is difficult to scale usesan RTB or a second MMU (with TLB) which derive the respective secondarycolor from the physical address.

Referring to FIG. 13, a further embodiment of a cache memory will beexplained, which in this case is a physically indexed cache memory.

The idea of controlling the cache allocation not only via the address,but also via a bit of information contained in the page table entries inaddition to the physical address, may also be implemented for physicallyindexed caches. It is true that this does not speed up the individualcache access in case of a hit, but it allows for a better exploitationand a higher hit rate because of a reduction of clashes. This variant isparticularly interesting in the context of second level caches.

The additional index c'" used for indexing besides the address r, may bereferred to as the tertiary color according to the terminology usedabove. The tertiary color can (but does not have to) be a wider bitfield than the above mentioned secondary color. It can also be identicalwith the secondary color or contain the same as a part thereof (ofcourse, the entire scheme also works exclusively with the tertiarycolor, i.e. without the secondary color).

The MMU or the TLB supplies the physical address r and the tertiarycolor c'" (see FIG. 13). In the map function, the tertiary color c'" islogically linked (combined) with the cache index portion of the physicaladdress r used for the cache indexing. Simple logic linkages are, forexample:

1. Replacing a portion of r with c'".

2. Exclusive-ORing a portion of r with c'".

3. Adding a portion of r and c'".

What is claimed is:
 1. A method of addressing a cache memory device forstoring data, comprisinga one-way or multi-way set-associative cachememory that is indexed by predetermined bits of a multi-bit virtualaddress (v) comprising a cache index portion (i') for addressing one ofa plurality of cache entries of the cache memory, which each comprisesat least one tag (r_(i), c_(i)) and at least one data field (d'), and apage number address portion (vpn) representing a virtual page number,which includes group information (c) specifying one of a plurality ofgroups to which the virtual page represented by the page number addressportion (vpn) of the virtual address (v) belongs, the virtual address(v) being translatable into a multi-bit physical address to whichprimary and secondary group information (c', c") are associated, thecache memory comprising at least one tag comparator for comparing thetag or predetermined bits of the tag of a cache entry, indexed by meansof the cache index portion (i') and the group information of the virtualaddress (v) or the primary or secondary group information, withpredetermined bits (r', c') of a physical address translated from thevirtual address, wherein cache addressing is attempted with thefollowing steps:a) the cache memory is indexed using the cache indexportion (i') and the group information (c) of the virtual address (v),one cache entry being addressed per way of the cache memory, b) in theassociated tag comparators, the tags (r_(i), c_(i)), or theirpredetermined bits, of all cache entries thus addressed are compared tothe predetermined bits (r', c') of the physical address translated fromthe virtual address (v), c) if there is a tag (r_(i), c_(i)) matchingpredetermined bits (r', c') of the physical address, there is a cachehit and the cache address operation is terminated, it being possible fordata to be written into and read out from the data field (d) specifiedby this tag, d) if, in step b), there is no match, the cache memory isindexed using the cache index portion (i') of the virtual address (v)and the secondary group information (c") and the steps b) and c) areexecuted for the cache entry or entries thus addressed, e) if again nomatch is obtained in step b), a cache miss is given and the cacheaddress operation is terminated.
 2. The method of claim 1, characterizedin that a translation lookaside buffer (TLB) unit of a memory managementunit (MMU) is provided for the translation of a virtual address into aphysical address, which, in addition to the physical address or parts ofthe physical address, also provides the primary and secondary groupinformation (c', c") associated thereto.
 3. The method of claim 2,characterized in that upon a cache miss, also the primary and secondarygroup information (c', c") for the physical addresses stored in the TLBunit are determined using page tables.
 4. The method of claim 1,characterized in that step d) is executed only if the secondary groupinformation differs from the group information.
 5. The method of claim1, characterized in that, following step b) which is executed for thefirst time or according to step d), the following steps are performed:e)if, in step b), there is no match, the cache memory is indexed using thecache index portion (i') of the virtual address (v) and the primarygroup information (c') of the physical address translated from thevirtual address (v), and the steps b) and c) are executed for the cacheentry or entries thus addressed, and f) if again no match is obtained instep b), a cache miss is given and the cache address operation isterminated.
 6. The method of claim 5, characterized in that step e) isexecuted only if the primary group information differs from both thegroup information and the secondary information.
 7. The method of claim5, characterized in that after the first execution of step c), step e)is executed first, followed by step d).
 8. The cache memory device ofclaim 5, characterized in that a decision device is provided, by meansof which it is decided whether, following the first execution of stepc), step e) is to be executed first, followed by step d), or whetherstep d) is to be executed first, followed by step e).
 9. The method ofclaim 8, characterized in that the decision device comprises arandom-check generator.
 10. The method of claim 8, characterized in thatthe decision device takes previous cache hits into consideration for thecurrent virtual address and makes the decision in dependence thereon.11. The method of claim 1, characterized in that in a multi-processorsystem with a bus and at least one cache memory, the bus also transmitsthe primary and/or the secondary group information, besides data andphysical addresses.